Many computer systems include processors having specialized arithmetic circuitry to operate on floating point numbers. Specialized circuitry is required because, unlike fixed-point numbers, floating point numbers have two components: a fractional or normalized component called a mantissa, and an exponent. Before two floating point numbers can be added or subtracted, the mantissas must be adjusted to account for the difference between the exponents.
FIG. 1 is a diagram of a prior-art circuit 5 for adding two floating point numbers, FPN1 and FPN2. Each of the floating point numbers FPN1 and FPN2 includes an exponent, a mantissa and a sign bit (not shown) which represent a numeric value as follows: EQU value=2.sup.(exponent-implied offset) .times.(1+mantissa).times.(-1).sup.sign bit.
The circuit 5 subtracts the exponents of FPN1 and FPN2 from one another in respective subtraction circuits 6 and 7. The positive difference between the exponents is then selected to indicate the number of bits by which the mantissa of the floating point number having the smaller exponent is to be right-shifted. Because the exponent indicates a power of two by which the mantissa is multiplied, right shifting the mantissa of a floating point number effectively increments its exponent. Consequently, right-shifting a mantissa by a number of bits equal to the positive difference between exponents effectively equalizes the exponents of the two floating point numbers FPN1 and FPN2. Note that the implied offsets in exponents EXP1 and EXP2 cancel one another when the exponents are subtracted.
After one of the mantissas has been right-shifted, it is added to the unshifted mantissa to produce a sum of mantissas. The sum of mantissas and the larger of the exponents are then output as a floating point sum of the numbers FPN1 and FPN2. The floating point sum may be normalized by later circuit stages.
One disadvantage of the prior art circuit 5 is that two separate subtraction operations are performed to obtain a positive difference between exponents. Each subtraction operation requires implementation logic which increases the overall transistor count required to implement the circuit 5. When implemented in an integrated circuit, increased transistor count translates to increased power consumption, circuit die size and fabrication cost.